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enpirion ? power datasheet en5364qi 6a powersoc voltage mode synchronous buck pwm dc - dc converter w ith integrated inductor description the en5364qi is a power supply on a chip (pwrsoc) dc to dc converter with integrated inductor, pwm controller, mosfets, and compensation providing the smallest possible solution size in a 68 pin qfn module. the switching frequency can be synchronized to an external clock or other en5364qis with the added capability of phasing multiple en5364qis as desired . other features include precision e nable threshold, pre - bias monotonic start - up, m argining , and parallel operation. en5364qi is specifically designed to meet the precise voltage and fast transient requirements of present and future high - performance applications such as set - top boxes/hd dvrs, lan/san adapter cards, audio/video equipment, optical networking, multi - function printers, test and measurement, embedded computing, storage, and servers. advanced circuit techniques, ultra high switching frequency, and very advanced, high - density, integrated circuit and proprietary inductor technology deliver high - quality, ultra compact, non - isolated dc -dc conversion. operating this converter requires very few external components. the altera enpirion integrated inductor solution significantly helps to reduce noise . the complete power converter solution enhances productivity by offering greatly simplified board design, layout and manufacturing requirements. all altera enpirion products are rohs compliant and lead - free manufacturing environment compatible . typical application circuit v out v in vfb 47f 47f 15nf vout enable agnd ss pvin avin pgnd pgnd figure 1 : typical application schematic features ? integrated inductor, mosfets, controller in a 8 x 1 1 x 1.85mm package ? wide input voltage range of 2.375v to 6.6 v. ? > 20w continuous output power. ? high efficiency, up to 93%. ? output voltage margining ? monotonic output voltage ramp during start - up with pre - biased loads. ? precision enable pin for accurate sequencing of power converters and power ok signal. ? programmable soft - start time. ? soft shutdown. ? 4 mhz operating frequency with a bility to synchroniz e to an external system clock or other en5364 ? s. ? p rogrammable phase delays between synchronized units to allow reduction of input ripple. ? master/slave configuration for paralleling multiple en5364 ? s for greater power output. ? under voltage lockout, over - current, short circuit, and thermal protection ? rohs compliant, msl level 3, 260c reflow . 1 www.altera.com/enpirion 03544 october 11, 2013 rev e
e n5364qi applications ? point of load regulation for low - power processors, network processors, dsps, fpgas, and asics ? low voltage, distributed power architectures with 2.5v, 3.3v or 5v, 6v rails ? computing, b roadband, networking, lan/wan, optical , test & measurement ? a/v, high density cards, storage, dsl, stb, dvr, dtv, industrial pc ? beat frequency sensitive applications ? a pplications requiring monotonic start - up with pre - bias ? ripple voltage sensitive applications ? noise sensitive applications ? pin compatible with en5394qi (9a) ordering information part number temp rating (c) package en5364qi - 40 to +85 68 - pin qfn t& r EVB-EN5364QI qfn evaluation board pin configuration pgnd pgnd pgnd pgnd vout vout vout vout vout vout vout vout vout nc nc pgnd pgnd pgnd pgnd pgnd vsense mar2 mar1 s_delay ss ocp_adj eaout vfb agnd pok avin enable en_pb m/s en5364qi nc nc nc nc nc nc nc nc nc nc(sw) nc(sw) pgnd pgnd pgnd pgnd pgnd pgnd pgnd pvin 66 68 67 63 65 64 60 62 61 57 59 58 54 56 55 53 52 50 51 18 16 17 21 19 20 24 22 23 27 25 26 30 28 29 31 32 34 33 s_in s_out nc nc nc nc pvin pvin pvin pvin pvin pvin pvin pvin pvin 1 4 3 6 5 8 7 10 9 12 11 14 13 15 2 49 46 47 44 45 42 43 40 41 38 39 36 37 35 48 69 pgnd thermal pads 70 pgnd figure 2: pinout diagram (top view ) . all perimeter pins must be soldered to pcb. 2 www.altera.com/enpirion 03544 october 11, 2013 rev e
en5364qi pin descriptions pin n am e function 1 - 4 , 27- 33, 64 - 68 pgnd input/output power ground. connect these pins to the ground electrode of the input and output filter capacitors. see vout and pvin descriptions for more details. 5- 13 vout regulated converter output. connect to the load, and place output filter capacitor(s) between these pins and pgnd pins 1 - 4 and 64 - 68. 14- 24, 44- 47 nc no connect: these pins must be soldered to pcb but not be electrically connected to each other or to any external signal, voltage, or ground. t hese pins may be connected internally. failure to follow this guideline may result in device damage. 25- 26 nc( sw ) no connect: these pins are internally connected to the common switching node of the internal mosfets. they must be soldered to pcb but not be electrically connected to any external signal, ground, or voltage. failure to follow this guideline may result in device damage. 34- 43 pvin input power supply. connect to input power supply , place input filter capacitor (s) between these pins and pgnd pins 27 - 33. 48 s_out clock output. depending on the mode, either a c lock signal or the pwm signal is output on this pin. these signals are delayed by a time that is related to the resistor connected between s_d elay and agnd. leave this pin floating if not needed. 49 s_in clock input. depending on the mode, this pin accepts either an input clock to synchronize the internal switching frequency or the s_out signal from another en5364qi. leave this pin floating if it is not used. 50 m/s this is a ternary input. floating the pin disables parallel operation. a low level configures the device as master and a high level configures the device as a slave. 51 en_pb this is the enable pre - bias input. when this pin is pulled high, the device will support monotonic start - up under a pre - bi as ed load. there is a 150k ? pull - down on this pin. 52 enable this is the device enable pin. a high level enables the device while a low level disables the device. 53 avin input power supply for the controller. needs to be connected to v in at a quiet point. 54 pok power ok is an open drain transistor for power system state indication. pok is a logic high when vout is with - 10% to +20% of vout nominal. being a n open drain output allows several devices to be wired to logically and the func tion. size pull - up resistor to limit current to 4ma when pok is low. 55 agnd ground return for the controller. needs to be connected to a quiet ground. 56 vfb external feedback input. the feedback loop is closed through this pin. a voltage divider at v out is used to set the output voltage. the mid - point of the divider is connected to vfb . the control loop regulates to make the vfb node voltage 0.6v . 57 ea out optional error amplifier out put. allows for customization of the control loop. 58 ocp_adj when this pin is pulled to agnd, the overcurrent protection trip point is increased by approximately 30%. leave floating for default ocp threshold (see electrical characteristics table). tie this pin to agnd for pin compatibility with the en5394. 59 ss a soft - start capacitor is connected between this pin to agnd. the value of the capacitor controls the soft - start interval and startup time. 60 s_delay a resistor is connected between this pin and agnd. the value of the resistor controls the delay in s_out. this pin can be left floating if the s_out function is not used. 61- 62 mar1 , mar2 these are 2 ternary input pins. each pin can be a logical lo, logical hi or float condition. 7 of the 9 states are used to modulate the output voltage by 0%, 2.5 %, 5 % or 10% . the 8th state is used to by - pass the delay in s_out. see functional description section. 63 vsense this pin senses vout when the device is placed in the ba c k - feed (or pre - bias) mode. 69, 70 pgnd device thermal pads to be connected to the system gnd plane. see layout recommendations section. 3 www.altera.com/enpirion 03544 october 11, 2013 rev e
en5364qi absolute maximum ratings caution: absolute maximum ratings are stress ratings only. functional operation beyond recommended operating conditions is not implied. stress beyond absolute maximum ratings may caus e permanent damage to the device. exposure to absolute maximum rated conditions for extended periods may affect device reliability. parameter symbol min m ax units voltages on pvin, avin, vout v in - 0.5 7.0 v voltages on vsense, en able , en_pb , pok, - 0.5 v in + 0.3 v voltages on vfb , eaout, ss, s_in, s_out , ocp_adj - 0.5 2.7 v voltages on mar1, mar2, m/s - 0.5 3.6 v storage temperature range t stg - 65 150 c maximum operating junction temperature t j - abs m ax 150 c reflow temp, 10 sec, msl3 jedec j - std - 020a 260 c esd rating (based on human body model) 2000 v recommended operating conditions parameter symbol min m ax units input voltage range v in 2.375 6.6 v output voltage range v out 0. 60 v in ? v do ? v output current i load 0 6 a operating ambient temperature t a - 40 +85 c operating junction temperature t j - 40 +125 c ? v do ( drop - out voltage) is defined as (i load x dropout resistance). please see electrical characteristics table. thermal characteristics parameter symbol typ units thermal resistance: junction to ambient (0 lfm) ? ? 4 www.altera.com/enpirion 03544 october 11, 2013 rev e
en5364qi electrical characteristics note: v in =5.5v over operating temperature range unless otherwise noted. typical values are at t a = 25c. parameter symbol comments min typ m ax units input voltage v in 2.375 6.6 v under voltage lock out threshold v uvlo r v uvlof v in increasing v in decreasing 2.2 2.1 v shut - down supply current i s enable=0v 250 a feedback pin voltage v fb 2.375v vin ? 2.375v v 6.6v ? 0a iload 6a ? ? c temp 85 ? rise time accuracy 1 ? ? 2.375v v 6.6 a switching frequency f switch free running frequency 4 mhz external s_in clock frequency lock r ange f pll_lock frequency range of s_in input clock 3.6 4.4 mhz s_in threshold ? low v s_in _lo s_in clock low level 0.8 v s_in threshold ? high v s_in _ hi s_in clock high level 1.8 2.5 v s_out threshold ? low v s_out _lo s_out clock low level 0.5 v s_out threshold ? high v s_out _ hi s_out clock high level 1.8 v s_in duty cycle for external synchronization 1 sy dc _sy nc m/s pin float or low 20 80 % s_in duty cycle for parallel operation 1 sy dc _pwm m/s pin high 10 90 % phase delay vs. s_delay resistor value del delay in ns / k ? ? - @ 4 mhz switching frequency 2 3 ns 5 www.altera.com/enpirion 03544 october 11, 2013 rev e
en5364qi phase delay between s_in and s_out 1 del phase delay programmable via resistor connected from s_delay to agnd. 20 150 ns phase delay between s_in and s_out 1 del delay by - pass mode (mar1 floating, mar2 high) 10 ns phase delay accuracy 1 - 20 20 % pre - bias level v pb allowable pre - bias as a fraction of programmed output voltage (subject to a minimum of 300mv) 20 85 % non - monotonicity v pb_nm allowable non monotonicity 50 mv pok lower threshold as a percent of v out 3 pok lt v out rising v out falling 92 90 % pok upper threshold as a percent of v out 3 pok ut v out rising v out falling 120 115 % p ok falling edge deglitch delay 4 60 s pok output low voltage v pokl with 4ma current sink into pok 0.4 v pok output high voltage v pokh 2.375v v 6.6v ? ? v in = 5.0v, r e xt = 24.9 k? v in = 6.6v, r e xt = 49.9 k ? 50 70 100 85 a binary input logic low threshold 6 v b- low 0.8 binary input logic high threshold 6 v b- high 1.8 notes : 1. parameter guaranteed by design. 2. maximum output current may need to be de - rated, based on operating condition, to meet t j requirements. 3. pok threshold when v out is rising is nominally 92%. this threshold is 90% when v out is falling. after crossing the 90% level, there is a 256 clock cycle (~50us) delay before pok is de - asserted. the 90% , 92% , 115%, and 120% levels are nominal values. expect these thresholds to vary by 3 %. 4. on the falling edge of vout below 90% of programmed value, pok response is delayed for the duration of the deglitch delay time. any vout glitch shorter than the deglitch time is ignored . 5. m/s, mar1, and mar2 are ternary. ternary pins have three logic levels: high, float, and low. these pins are only meant to be strapped to v in through an external resistor, strapped to gnd, or left floating. their state cannot be changed while the device is on. 6. binary input pins are en_pb and ocp_adj. 6 www.altera.com/enpirion 03544 october 11, 2013 rev e
en5364qi typical performance characteristics efficiency v in = 3.3v v out (from top to bottom) = 2.5, 1.8, 1.2, 1.0 v efficiency v in = 5.0v v out (from top to bottom) = 3.3, 2.5, 1.8, 1.2, 1.0v output ripple: v in = 3.3 v, v out = 1.2v , iout = 6a c in = 2 x 22 output ripple: v in = 3.3 v, v out = 1.2v , iout = 6a c in = 2 x 22 output ripple: v in = 5 .0 v, v out = 1.2v , iout = 6a c in = 2 x 22 output ripple: v in = 5 .0 v, v out = 1.2v , iout = 6a c in = 2 x 22 30 40 50 60 70 80 90 0 1 2 3 4 5 6 load (amps) efficiency (%) v in = 5v 20 30 40 50 60 70 80 90 0 1 2 3 4 5 6 load (amps) efficiency (%) 20 mhz bw limit 500 mhz bw 20 mhz bw limit 500 mhz bw 7 www.altera.com/enpirion 03544 october 11, 2013 rev e
en5364qi load transient: v in = 5.0v, v out = 1.2v ch.1: v out , ch. 4: i l oad 0 ? 10a/ s) c in ? load transient: v in = 3.3 v, v out = 1.2v ch.1: v out , ch. 4: i l oad 0 ? 10a/ s) c in ? power up/down at no load: v in /v out = 5.0v/1.2v , 15nf soft - start capacitor, ch.1: enable, ch. 2 : v out , ch. 3 ; pok power up/down into 0.2 ? delay vs. s_delay resistance enable lockout operation ch.1: enable, ch2: v out delay vs. s_delay resistance 0 20 40 60 80 100 120 140 160 180 0 20 40 60 80 100 s_delar r (kohm) delay (ns) 8 www.altera.com/enpirion 03544 october 11, 2013 rev e
en5364qi block diagram (+) (-) error amp v out p-drive n-drive uvlo thermal limit current limit soft start pll / sawtooth generator (+) (-) pwm comp pvin enable compensation network bandgap reference pgnd vfb eaout s_out ss reference voltage selector over voltage power good logic pok s_in mar1 mar2 eaout en_pb digital i/o m_s to pll mar1/2 nc(sw) figure 3. system block diagram functional description synchronous buck converter the en536 4qi is a synchronous, programmable power supply with integrated power mosfet switches and integrated inductor. the nominal input voltage range is 2. 375- 6.6 v. the output voltage is programmed using an external resistor divider network. the feedback control loop is a type iii , voltage - mode , and the device uses a low - noise pwm topology. up to 6a of contin uous output current can be drawn from this converter. the 4 mhz operating frequency enables the use of small - size input and output capacitors. the power supply has the following protection features: ? o ver - current protection with hiccup mode. ? short circuit pr otection. ? thermal shutdown with hysteresis. 9 www.altera.com/enpirion 03544 october 11, 2013 rev e
en5364qi ? under - voltage lockout circuit to disable the converter output when the input voltage is less than approximately 2.2v enable operation the enable pin provides a means to start normal operation or to shut down the device. a logic high will enable the converter into normal operation. when the enable pin is asserted (high) the device will undergo a normal soft start. a logic low will disable the converter. a logic low will power down the device in a controlled manner and the device is subsequently shut down. the device will remain shut - down for the duration of the enable lockout time (see electrical characteristics table) . if the enable signal is re - asserted during this time, the device will power up with a normal soft - start at the end of the enable lockout time. the enable threshold is a precision analog voltage rather than a digital logic threshold. precision threshold along with choice of soft - start capacitor helps to accurately sequence multiple power supplies in a system. frequency synchronization the switching frequency of the dc/dc converter can be phase - locked to an external clock source to move unwanted beat frequencies out of band. to avail this feature, the ternary input m/s pin should be floating or pulle d low. the internal switching clock of the dc/dc converter can then be phase locked to a clock signal applied to s_in pin. an activity detector recognizes the presence of an external clock signal and automatically phase - locks the internal osci llator to this external clock. phase - lock will occur as long as the input clock frequency is within 10% of the free running frequency (see electrical characteristics table) . when no clock signal is present, the device reverts to the free running frequency of the internal oscillator. the external clock input may be swept between 3.6 mhz and 4.4 mhz at repetition rates of up to 10 khz in order to reduce emi frequency components. master / slave parallel operation multiple en5364qi devices may be connected in parallel in a master/slave configuration to handle load currents greater than device maximum rating . the device is set in master mode by pulling the ternary m/s pin low or in slave mode by pulling m/s pin high to v in through an external resistor . when this pin is in float state, parallel operation is not possible. in master mode, the internal pwm signal is output on the s_out pin. this pwm signal from the master can be fed to one or more slave devices at its s_in input. the slave device acts like an extension of the p ower fets in the master. as a practical matter, paralleling more than 4 devices may be very difficult from the view point of maintaining very low impedance in v in and v out lines. the table below summarizes the different configurations for the s_in and s_out pins depending on the condition of the m/s pin: when m/s pin i s: high (slave) low (master) float s_in input should be: s_out from master external sync input if needed ( nc for internal clock ) s_out i s equal to (subject to s_delay): same duty cycle as s_in same duty cycle as internal pwm s_in or internal clock please contact altera power applications support for more information on master / slave operation. phase delay in all cases, s_out can be delayed with respect to internal switching clock or the clock applied to s_in. multiple en5364qi devices on a system board may be daisy chained to reduce or eliminate input ripple as well as avoiding beat frequency components. th e en5364qis can all be phase locked by feeding s_out of one device into s_in of the next device in a daisy chain. all the switchers now run at a common frequency. the delay is controlled by the value of a resistor connected between s_d elay and agnd pins. the magnitude of this delay as a function of s_ delay resistor is shown in the electrical c haracteristics table. see figures 6 and 7 for an example of using phase delay. margining using mar1 and mar2 pins, t he nominal output 10 www.altera.com/enpirion 03544 october 11, 2013 rev e
en5364qi voltage can be increased / decrea sed by 2.5 , 5 or 1 0 % for system compliance, reliability or other tests. the pok threshold voltages scale with the margined output voltages. the foll owing table provides the possible combinations: m ar 1 m ar 2 output modulation float float 0% low low - 2.5% high low +2.5% low high - 5% high high +5% low float - 10% high float +10% float high 0%, delay byp ass float low reserved note: low means t ie to gnd. high means t ie to v in as shown in figure 5. as shown above, when mar1 is floating, and mar 2 is high, the device enters the delay bypass mode. in this mode, the delay from the internal clock or s_in to s_out is almost eliminated (see electrical characteristics table). soft - start operation the ss pin in conjunction with a small external capacitor between this pin and agnd provides the soft start function to limit the in - rush current during start - up. during start - up of the converter the reference voltage to the error amplifier is gradually increased to its final level as an internal curren t source of typically 10ua charges the soft start capacitor . the typical soft - start time for the output to reach regulation voltage , from when avin > v uvlo and e nable crosses its logic high threshold, is given by: t ss = (c ss * 65k ) 25% where the soft -s tart time t ss is in seconds and the soft - start capacitance c ss is in farads . typically, around 15nf is recommended. the soft - start capacitor should be between 4.7nf and 100nf. a proper choice of ss capacitance can be used advantageously for power supply sequencing using the precision enable threshold. during a soft - start cycle, when the soft - start capacitor voltage reaches 0.60v, the output has reached its programmed regulation range. note that the soft - start current source will continue to charge the ss capacitor beyond 0.6v. during normal operation, the soft - start capacitor will charge to a final value of ~1.5v. soft - shutdown operation when the enable signal is de - asserted, the soft - start capacitor is discharged in a controlled manner. thus the output v oltage ramps down gradually. the internal circuits are kept active for the duration of soft - shutdown, thereafter they are deactivated. pre - bias operation when en_pb is asserted, the device will support a monotonic output voltage ramp if the output capacito r is charged to a pre - bias level. proprietary circuit ensures the output voltage ramps monotonically from pre - bias voltage to the programmed output voltage. monotonic start -up is guaranteed by design for pre - bias voltages between 20% and 85% of the program med output voltage. this feature is not supported when enable is tied to v in . pok operation the pok signal indicates if the output voltage is within a specified range. the pok signal is asserted when the rising output voltage crosses 92% (nominal) of the p rogrammed output voltage. pok is de - asserted ~50us (256 clock cycles) after the falling output voltage crosses 90% (nominal) of the programmed voltage. pok is also de - asserted if the output voltage exceeds 120% of the programmed output. if the feedback loo p is broken, pok will remain de - asserted (o utput < 92% of programmed value ), and the output voltage will equal the input voltage. if however, there is a short across the pfet, and the feedback is in place, pok will be de - asserted as a n over voltage conditi on. t he power nfet is also turned on , resulting in a lar ge input supply current. this in turn is expected to trip the ocp of the en5364qi input power supply. pok is an open drain output. it requires an external pull up. multiple en5364qi?s pok pins may be connected to a single pull up. the open drain nfet is designed to sink up to 4ma. the 11 www.altera.com/enpirion 03544 october 11, 2013 rev e
en5364qi pull - up resistor value should be chosen accordingly for when pok is logic low. input under - voltage lock - out (uvlo) when the input voltage is below a required voltage lev el (v uvlo ) for normal operation, the converter switching is inhibited. the lock - out threshold has hysteresis to prevent chatter. uvlo is implemented to ensure that operation does not begin before there is adequate voltage to properly bias all internal circ uitry. over - current protection (ocp) the current limit and short - circuit protection is achieved by sensing the current flowing through a sense p - fet. when the sensed current exceeds the current limit, both nfet and pfet switches are turned off. if the over - current condition is removed, the over - current protection circuit will re - enable the pwm operation. if the over - current condition persists, the circuit will continue to protect the device. the ocp trip point is nominally set to 17 5% of maximum rated load. in the event the ocp circuit trips, the device enters a hiccup mode. the device is disabled for ~ 10msec and restarted with a normal soft - start. this cycle can continue indefinitely as long as the over current condition persists. during soft - start at power up or fault recovery, the hiccup mode is disabled and the device has cycle -by - cycle current limiting. thermal overload protection thermal shutdown will disable operation when the junction temperature exceeds approximately 150oc. once the junction temperature drops by approximately 20oc, the converter will re - start with a normal soft - start. compensation the en5364 uses of a type iii compensation network. most of this network is integrated. however a phase lead capacitor is required in parallel with upper resistor of the external divider network (see figure 4). this network results in a wide loop bandwidth and excellent load transient performance. it is optimized for around 50 f of output filter capacitance at the voltage sensing point. additional decoupling capacitance may be placed beyond the voltage sensing point outside the control loop. v oltage - mode operation provides high noise immunity at light load. further, v oltage - mode control provides superior impedance matching to ics processed in sub 90nm technologies. in exceptional cases modifications to the compensation may be required. the en5364qi provides the capability to modify the control loop response to allow for customization for specific applications. for more information, contact altera power applications support. application information output voltage programming the en5364 output voltage is determined by the voltage presented at the vfb pin. this voltage is set by way of a resistor divider between v out and agnd with the midpoint going to vfb. a phase lead capacitor c a is also required for stabilizing the loop. figure 4 shows the required components and the equations to calculat e their values . please note the equations below are written to optimize the control loop as a function of input voltage. figure 4: output voltage resistor divider and phase - lead capacitor calculation. the equa tions need to be followed in the order written above. v out r a c a r b v fb ? ? ? ? ? ? ? ? ? = ? = ? = ? nominal 0.6v is value. calculated than lower value standard closest to down c round ) f/ in /r (c ) in (value a aa fb fb out a fb b a a a v vv rv r r c vin r )( 1072.4 000,30 6 12 www.altera.com/enpirion 03544 october 11, 2013 rev e
en5364qi input capacitor selection the en536 4 qi requires between 20-40 uf of input capacitance. low esr ceramic capacitors are required with x5r or x7r dielectric formulation. y5v or equivalent dielectric formula tions must not be used as these lo se capacitance with frequency, temperature and bias voltage. in some applications, lower value ceramic capacitors may be needed in parallel with the larger capacitors in order to provide high frequency decoupling. recommended input capacitors description mfg p/n 10uf, 10v, 10% x7r, 1206 (2 - 4 capacitors needed) murata grm31cr71a106ka01l taiyo yuden lmk316b7106kl -t 22uf, 10v, 20% x5r, 1206 (1 - 2 capacitors needed) murata grm31cr61a226me19l taiyo yuden lmk316bj226ml - t 47uf, 6.3v, 20% x5r, 1206 (1 capacitor needed) murata grm31cr60j476me19l taiyo yuden jmk212bj476ml -t output capacitor selection the en536 4 has been optimized for use with about 50 f of output filter capacitance . up to 100 f can be placed at the voltage sensing point . additional capacitance may be placed beyond the voltage sensing point outside the control loop. for the output filter, l ow esr x5r or x7r ceramic capacitors are required . y5v or equivalent dielectric formulations must not be used as these lose capacitance with frequenc y, temperature and bias voltage . recommended output capacitors description mfg p/n 47uf, 6.3v, 20% x5r, 1206 (1 capacitor needed) murata grm31cr60j476me19l taiyo yuden jmk212bj476ml - t 10uf, 6.3v, 10% x5r, 0805 (optional 1 capacitor in parallel with 47uf above) murata grm21br60j106ke19l taiyo yuden jmk212bj106kg -t ou tput ripple voltage is primarily determined by the aggregate output capacitor impedance. at the 4 mhz switching frequency , the capacitor impedance, denoted as z, is comprised mainly of effective series resistance, esr, and effective series inductance, esl: z = esr + esl. placing multiple capacitors in parallel reduces the impedance and hence will result in lower ripple voltage . n total zzzz 1 ... 111 21 +++= output capacitor configuration typical output ripple (mvp - p) (as measured on en536 4 qi evaluation board) ? 1x 47uf 30 mv 1x47uf + 1x10uf 15mv ? 20 mhz bandwidth limit t ernary pin inputs the three ternary pins mar1, mar2, and m/s have three possible states. in the low state, the pins are to be tied to gnd. in the floating state, nothing is to be connected to the pins. in the high state, they are to be tied to v in through an external resistor r ext in order to limit the input current to the pin (see figure 5) . the electrical characteristics table lists , as a function of v in , some recommended values for r ext , and the resulting input currents . frequency sync & phase delay the en5364 can be synchronized to an external clock source or to another en5364 in order to eliminate unwanted beat frequencies. furthermore, two or more synchronized en5364?s can have a programmable phase delay with respect to each other to minimize input vol tage ripple and noise. an example of synchronizing three en5364?s with approximately equal phase delay between them is shown in figures 6 and 7. the lowest allowable value for the s_delay resistor is 10k ? . power up /down sequencing during power - up, enable should not be asserted before pvin, and pvin should not be asserted before avin. the pvin should never be powered when avin is off. during power 13 www.altera.com/enpirion 03544 october 11, 2013 rev e
en5364qi down, the avin should not be powered down before the pvin. tying pvin and avin or all three pins (avin, pvin, enable) together during power up or power down meets these requirements . figure 6: example of synchronizing multiple en5364qis in a daisy chain with phase delay. figure 7: example of a possible way to synchronize and use delays advantageously to minimize input ripple. r1 ~ 39k ? ? rext r1 100k r2 100k r3 3k d1 2.5v vin agnd to gates ic package vf ~ 2v 250 x1 en5364 p/avin p/agnd vfb s_in vout s_out s_delay x1_1 en5364 p/avin p/agnd vfb s_in vout s_out s_delay x1_2 en5364 p/avin p/agnd vfb s_in vout s_out s_delay vin r1 r2 r3 gnd r4 r5 c1 ou t1 r6 r7 c2 ou t2 r8 r9 c3 ou t3 ext_clk v drain - 1 v drain - 2 v drain - 3 delay ~ 140 14 www.altera.com/enpirion 03544 october 11, 2013 rev e
en5364qi layout recommendations figure 8: critical components and layer 1 copper for minimum footprint figure 8 above shows critical components and layer 1 traces of the recommended en5364 layout for minimum footprint with enable tied to v in . alternate enable configurations, and o ther small signal pins need to be connected and routed according to specific customer application. please see the gerber files at www.altera.com/enpirion for exact dimensions and other layers . recommendation 1: input and output filter capacitors should be placed on the same side of the pcb, and as close to the en536 4 q i package as possible . they should be connected to the device with very short and wide tra ces . do not use thermal reliefs or spokes when connecting the capacitor pads to the respective nodes . the +v and gnd traces between the capacitors and the en5364qi should be as close to each other as possible so that the gap between the two nodes is minimi zed , even under the capacitors. recommendation 2: the system ground plane referred to in recommendations 2 and 3 should be the first layer immediately below the surface layer. this ground plane should be continuous and un - interrupted below the converter a nd the input/output capacitors. recommendation 3 : the large and small thermal pads underneath the component must be connected to the system ground plane through as many vias as possible. the drill diameter of the vias should be 0.33mm , and the vias must ha ve at least 1 oz. copper plating on the inside wall, making the finished hole size around 0.20 - 0.26mm . do not use thermal reliefs or spokes to connect the vias to the ground plane. this connection provides the path for heat dissipation from the converter. please see figures: 8, 9, and 10. recommendation 4 : multiple small vias (the same size as the thermal vias discussed in recommendation 3) should be used to connect ground terminal of the input capacitor and output capacitors to the system ground plane. it is preferred to put these vias along the edge of the gnd copper closest to the +v copper. these vias connect the input/output filter capacitors to the gnd plane, and help reduce parasitic inductances in the input and output current loops. recommendation 5 : avin is the power supply for the small - signal control circuits. it should be connected to the input voltage at a quiet point. in figure 8 this connection is made at the input capacitor. recommendation 6 : the layer 1 metal under ? ? ca is used for loop compensation. ? css is the soft - start capacitor. ? agnd via is also a test point. ? test point added for eaout. 15 www.altera.com/enpirion 03544 october 11, 2013 rev e
en5364qi the device must not be more than shown in figure 8. see the section regarding exposed metal on bottom of package. as with any switch - mode dc/dc converter, try not to run sensitive signal or control lines underneath the converter package on other layers. recommendation 7: the v out sense point should be just after the last output filter capacitor. keep the sense trace short in order to avoid noise coupling into the node. recommendation 8 : keep r a , c a , and r b close to the vfb pin (see figures 4 and 8). the vfb pin is a high - impedance, sensitive node. keep the trace to this pin as short as possible. whenever possible, connect r b directly to the agnd pin instead of going through the gnd plane. thermal considerations the altera enpirion en 5364 q i dc -dc converter is packaged in an 11 x 8 x 1.85mm 68- pin qfn package. the qfn package is constructed with copper lead frames that have exposed thermal pads. the recommended maximum junction temperature for continuous operation is 125c. continuous o peration above 125c will reduce long - term reliability. the device has a thermal overload protection circuit designed to shut it off at an approximate junction temperature value of 150c. the silicon is mounted on a copper thermal pad that is exposed at th e bottom of the package. there is an additional thermal pad in the corner of the package which provides another path for heat flow out from the package . the thermal resistance from the silicon to the exposed thermal pad s is very low. in order to take advantage of this low resistance, the exposed thermal pad s on the package should be soldered directly on to a copper ground pad on layer 1 of the pcb . the pcb then acts as a heat sink. in order for the pcb to be an effective heat sink, the device thermal pad s should be coupled to copper ground planes using multiple vias (refer to layout r ecommendations section). the junction temperature, t j , is calculated from the ambient temperature, t a , the device power dissipation, p d , and the device junction -to - ambient thermal resistance, ja in c/w: t j = t a + (p d )( ja ) the junction temperature, t j , can also be expressed in terms of the device case temperature, t c , and the device junction -to - case thermal resistance, jc in c/w, as follows : t j = t c + (p d )( jc ) the device case temperature, t c , is the temperature at the center of the larger exposed thermal pad at the bottom of the package. the device junction -to - ambient and junction-to - case thermal resistances, ja and jc , are shown in the thermal characteristics table. the jc is a function of the device and the 6 8- pin qfn package design. the ja is a function of jc and the user?s system design parameters that include the thermal effectiveness of the customer pcb and airflow. the ja value shown in the thermal characteristics table is for free convection with the device heat sunk (through the thermal pads ) to a copper plated four - layer pc board with a full ground and a full power plane following jedec eij/jesd 51 standards. the ja can be reduced with the use of forced air convection. because of the strong dependence on the thermal effectiveness of the pcb and the system design, the actual ja value will be a function of the specific application. when operating on a board with the ja of the thermal characteristics table, no thermal deratings are needed to operate all the way up to maximum output current . 16 www.altera.com/enpirion 03544 october 11, 2013 rev e
en5364qi design considerations for lead -frame based modules exposed metal on bottom o f package lead- frame s offer many advantages in thermal performance, in reduced electrical lead resistance, and in overall foot print. however, they do require some special considerations. in the assembly process lead frame construction requires that, for mechanical support, some of the lead - frame cantilevers be exposed at the point where wire- bond or internal passives are attached. this results in several small pads being exposed on the bottom of the package, as shown in figure 9. only the two thermal pad s and the perimeter p ads are to be mechanically or electrically connected to the pc board. the pcb top layer under the en536 4 qi should be clear of any metal (copper pours, traces, or vias) except for the two thermal pad s . the ?grayed - out? area in figure 9 represents the area that should be clear of any metal on the top layer of the pcb . any layer 1 metal under the grayed - out area runs the risk of undesirable shorted connections even if it is covered by soldermask . one exposed pad in the grayed - out area can have v in metal under it as noted in figure 9. figure 10 demonstrates the recommended pcb footprint for the en536 4 qi . figure 11 shows the package dimensions. figure 9: lead - frame exposed metal. grey area highlights exposed metal that is not to be mechanically or electrically connected to the pcb. v in copper covered by soldermask acceptable under this exposed pad. 17 www.altera.com/enpirion 03544 october 11, 2013 rev e
en5364qi pcb footprint and package dimensions figure 10: en5364 qi pcb footprin t ( top view) the solder stencil aperture for the thermal pad is shown in blue and is based on enpirion power product manufacturing specifications. 18 www.altera.com/enpirion 03544 october 11, 2013 rev e
en5364qi figure 11 . package dimensions contact information altera corporation 101 innovation drive san jose, ca 95134 phone: 408 -544-7000 www.altera.com ? 2013 altera corporation ? confidential. all rights reserved. altera, arria, cyclone, enpirion, hardcopy, max, megacore, nios, quartus and stratix words and logos are trademarks of altera corporation and registered in the u.s. patent and trademark office and in other countries. all other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. altera warrants performance of its semiconductor products to current specifications in accordance with altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. altera assumes no responsibility or liab ility arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by altera. altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. 19 www.altera.com/enpirion 03544 october 11, 2013 rev e

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